Developer Home Contents Search Feedback Support Intel(r)


CheckMate* Emulators For the Intel 80186 Family

Beacon Development Tools


Architecture:
Type :
Last Update:

Embedded Intel Architecture EX
Emulator
11/22/96 11:26:00 AM

Vendor Information



Tool Description:

The CheckMate II in-circuit emulator takes advantage of patented 1990's gate array and surface mount assembly technologies to deliver all the emulator features required today in a single low-profile, small foot print device. All CheckMate* emulators take full advantage of Intel's processor technology to insure true transparent and exact emulator functionality.
The emulator combines a robust, state machine driven bus event system and a wide and deep trace memory bugger to deliver next generation capability to the user. As you expect, CheckMate integrates into your existing development environment. We offer support for all Borland* and Microsoft* compilers as well as Intel compilers with the industry standard Paradigm/DEBUG source level debug interface.
The bus event system consists of four groups that each contain eight ADDRess/ADDR range, DATA and STATUS comparitor sets. Each event level or group has an independent 16-bit event pass counter and 8 independent Logic State Input channels. Within the group, each event is coupled independently to both the event counter and the LSI channels. This system makes it easy to identify even the most obscure execution faults.
The trace buffer captures 16K bus cycles of ADDRess, DATA, and STATUS along with the 16-bit timestamp and 8 Logic State Input channels. The trace display shows any combination of source, assembly and raw cycles interleaved for true execution history clarity, and can be fully qualified by any event in the Bus Event System. The timestamp uses 5 timebases - 100 nsec to 1 msec - that are independent of the target CLK; counter overflow is captured automatically to insure accurate long duration measurements. A special timestamp mode measures the MIN, MAX and MEAN interval time statistic.
The overlay RAM is 0-wait state at 25 MHz operation, and may be mapped across the entire target memory address space on 1 K boundaries. Each segment can be access protected.
CheckMate emulators have two different models to complete your development tool environment. Finally, you can fine tune development tool capabilities to your team's individual requirements.

Tool Features:

  • 5V and 3V Support From the Same Product

  • 10 Mbits Per Second Communications Speed

  • Fully supports Intel's ONCE (TM) Mode For Plug In and Run Operation

  • Truly Transparent to the Target

  • Does Not Use Interrupts or Any Memory Space

  • Paradigm DEBUG* Source Level Debug Interface Standard

  • Logic Analyzer Style Event System for Target Control and Trace Capture Logic

  • 25 MHz Target Operation

  • 16K Bus Cycles Trace Buffer

  • 1024K Overlay Memory

  • Development Platform(s):

    486 PC or above (386 PC min.), 4 MB RAM, Microsoft Windows* ot OS/2 Warp

    File Attachments:

    IA2_BD1.PDF - SolutionsIA Catalog Product Listing

    Supported Device Detail Matrix:

    Part & Package

    Availability

    80C186EA - 68ldPLCC
    80C186EB - 80ldQFP
    80L186EA - 68ldPLCC
    80L186EA - 80ldQFP

    NOW
    NOW
    NOW
    NOW



    Vendor Information:


    Beacon Development Tools

    9430 Research Blvd., Bldg. IV, Suite 310
    Austin , TX 78759
    USA
    (512) 338-9211

    Tech : (800) 769-9143
    Email : info@beacontools.com
    Fax : (512) 346-6382
    Toll Free : (800) 769-9143
    BBS : (512) 467-8947
    URL : http://www.beacontools.com

    Contact the vendor above for the latest Distributor information




    * Legal Information © 1998 Intel Corporation